Embodiments of the inventive subject matter generally relate to the field of signal processing devices and, more particularly, to a hybrid successive approximation analog-to-digital converter (ADC).
An ADC that employs a successive approximation register (SAR) referred to herein as a “SAR ADC” converts a continuous analog input signal into a discrete digital representation of the analog input signal. The SAR ADC executes binary search operations by comparing, at each iteration, the analog input signal against a threshold determined as part of the binary search operations. The SAR ADC generates a digital bit (at logic zero or at logic one) at each iteration based on the result of the comparison.